NVMe leverages the Peripheral Component Interconnect Express (PCIe) bus directly, not as a mere physical transport but as a native parallel fabric. The specification defines up to 65,535 I/O queues, each with a queue depth of 65,536 commands. In practice, this means a multi-core CPU can dedicate a distinct queue to each core, allowing commands to be submitted and completed without locking or inter-processor interrupts. This "multiple queue" model enables near-linear performance scaling with core count—a critical feature for modern server and client architectures.
: Defines the foundational protocol, including the register interface, command sets, and the submission/completion queue mechanism. nvme spec
: By sitting directly on the PCIe bus, the protocol reduces the number of CPU cycles required for each I/O operation. Physical vs. Logical Interface Physical vs
: Deep queue depths allow the SSD to process thousands of commands simultaneously, maximizing the bandwidth of the PCIe interface. the specification supports interrupt coalescing
NVMe defines a flexible interrupt architecture. The controller can generate Message Signaled Interrupts (MSI-X) for each completion queue, allowing the OS to route completions directly to the CPU core that issued the original command. This reduces cross-core cache coherence traffic and improves overall throughput. Furthermore, the specification supports interrupt coalescing, where the controller delays interrupt generation until a specified number of completions or a timeout occurs, balancing latency against CPU overhead.