The evolution of computer architecture is frequently bottlenecked by the speed at which subsystems communicate. In the early 1990s, the Parallel PCI bus replaced ISA and VESA Local Bus, offering a shared 32-bit parallel interface. However, as processor speeds outpaced bus frequencies, the limitations of parallel buses—specifically clock skew and crosstalk—became apparent. In 2003, the PCI-SIG introduced PCIe (then known as PCI Express or 3GIO).
PCIe 2.0, released in 2007, doubled the data transfer rate to 5 GT/s, increasing the bandwidth to 500 MB/s per lane. This revision also introduced support for multiple lanes (x4, x8, and x16), enabling higher-bandwidth connections. pci express revision
Unlike its parallel predecessor, PCIe utilizes a point-to-point topology. Each device has a dedicated connection (a "link") to the host, eliminating the bandwidth contention of the shared bus. The technology relies on "lanes"—differential pairs for transmitting and receiving data. A key design philosophy of PCIe is the doubling of data transfer rates with each major revision, alongside strict backward compatibility, ensuring that legacy hardware remains functional on newer mainboards. In 2003, the PCI-SIG introduced PCIe (then known
PCI Express Revisions Explained: What’s the Difference Between Gen 3, 4, 5, and 6? alongside strict backward compatibility